Oser Communications Group

Super Computer Show Daily Nov 20, 2014

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S u p e r C o m p u te r S h o w D a i l y 9 Th u r s d a y, N o ve m b e r 2 0 , 2 0 1 4 reliable solutions that operate at reduced performance. Moving the add- in cards to an external chassis that attaches to the server through the PCIe bus provides substantially more slots, power and cooling. The external chassis approach utilizes a high-performance host card that installs in the host server. In this way, physically smaller and lower cost servers can be utilized, and still have access to large quantities of compute and Flash storage resources. One Stop Systems ( Cont'd. from p. 1) OSS believes that the HDCA and FSA are the future within HPC. The OSS strategy leverages its strengths in PCIe over cable to help users utilize more of these key technologies to dramatically increase the performance of their HPC systems. By teaming with key industry leaders such as IBM, Intel and NVIDIA, OSS is expanding the limits of HPC. Visit One Stop Systems at booth #754. For more information, go to www.onestop systems.com, call 760-745-9883 or email sales@onestopsystems.com. About ASRock Rack Inc. ASRock Rack Inc., established in 2013, specializes in the field of cloud computing server hardware. While inheriting ASRock's design concepts, "Creativity, Consideration, Cost- effectiveness," the company is dedi- cated to bring the server industry out of the box thinking with the passion to innovate. Leveraged by ASRock's growing momentum and distribution channels, ASRock Rack ( Cont'd. from p. 1) this young and vibrant company tar- gets the booming market of cloud computing, and commits to serve the market with user friendly and eco friendly Do It Yourself server hard- ware, featuring flexible and reliable products. For further information, visit www.asrockrack.com. Visit ASRock Rack at booth #3558. For more product information, go towww.asrockrack.com/events/Enhanced Computing/index.html or email ASRockRack_marketing@asrockrack.com. projects was tantamount. With our reputation for a customer- based consult-architect-build approach, Silicon Mechanics was selected to replace the cluster. Working collabora- tively with the research facility, experts from Silicon Mechanics helped define the problem, offered multiple options, developed and built the best solution, and then supported the facility through the deployment and beyond. Since its installation, researchers at the facility have utilized the HPC for mathematical modeling on disease trans- Silicon Mechanics ( Cont'd. from p. 1) mission, collection of data from a variety of instruments, and genomics research, including studying how genomic muta- tions contribute to causing cancer. While the destruction caused by Hurricane Sandy was devastating, we at Silicon Mechanics are grateful for the opportuni- ty that resulted, allowing us to get involved in this organization's amazing research that has the potential to impact people throughout the world. Visit Silicon Mechanics at booth #2623. For more information, go to www.silicon mechanics.com, call 425-424-0000 or email info@siliconmechanics.com. partnerships seek to resolve more wide ranging problems involving the trans- portation of digital information. SCSD: Can you provide some insight into Ciena's current collaboration proj- ects taking place, like the SDN Testbed? RW: To accelerate the formation of an OPn ecosystem for the WAN and to provide an environment for Ciena cus- tomers and partners to conduct research, trials, demonstrations and experiments on emerging OPn tech- nologies, Ciena has teamed with R&E community partners Internet2, StarLight, CANARIE and ESnet to cre- ate an OPn test-bed. The test-bed fea- tures extensive and open network pro- grammability – using OpenFlow – and spanning packet, Layer 1 OTN and optical system control. It includes and is driven by a prototype, open architec- ture and multi-layer centralized control system, providing an abstracted north- bound API to business applications. The Ciena ( Cont'd. from p. 1) control system features prototype real- time analytics apps driving network resource and revenue optimization. For the first time, the OPn test-bed brought together the critical mass of piece parts of the future OPn platform for carrier-style WANs—allowing benefits to be clearly proven, and paths to adop- tion closely studied. SCSD: Can you provide a commercial networking technology in use today that was a direct result of collaboration with the R&E community? RW: R&E networks lead the industry in open, collaborative networking across many geographies and institu- tions. Often early adopters, these net- works serve as a proving ground for innovative technologies. Recently the R&E community has been vital in developing technologies such as terabit and 100G, coherent optical detection and Software-Defined Networking (SDN) to name a few. For more information, visit Ciena at booth #3315. TEST OF TIME AWARD TO BE AWARDED TO GRAPH PARTITIONING PIONEERS Bruce Hendrickson and Rob Leland of Sandia National Laboratories will receive the Supercomputing Conference's Test of Time Award at this year's conference for their paper, "A Multi-level Algorithm for Partitioning Graphs." Hendrickson, Affiliated Professor of Computer Science at University of New Mexico and Senior Manager for Extreme Scale Computing at Sandia National Laboratories, and Leland, Director of Computing Research at Sandia National Laboratories, were selected for their achievements in laying the inspira- tional groundwork for graph partition- ing. Published in 1995 in the Proceedings of Supercomputing, "A Multi-level Algorithm for Partitioning Graphs" has had a tremendous impact on parallel computing, as graph parti- tioning lies at the heart of numerous scientific computations and is actively used to this day. "The innovative methods so ele- gantly introduced in this paper repre- sented the starting point for a collection of popular partitioning and load-bal- ancing approaches, together with toolsets that have enabled scalable par- allelism for countless applications over the past two decades," says Ewing ("Rusty") Lusk, Argonne Distinguished Fellow Emeritus at Argonne National Laboratory. Multi-level graph partitioning is a method that partitions a series of small- er graphs and then propagates the result back to the original graph. Hendrickson and Leland were the first to develop this concept in their initial software, Chaco. Hendrickson and Leland's work served as the basis for many widely used libraries in the HPC community, which was almost solely due to the publication of this paper. "The idea of hierarchical graph partitioning, as introduced by Hendrickson and Leland, has proven essential, especially given the increased importance of unstructured meshes in science and engineering simulations," said Kathy Yelick, Associate Laboratory Director of Computing Sciences at the Lawrence Berkeley National Laboratory and Professor of Electrical Engineering and Computer Sciences at the University of California at Berkeley. "Today, this methodology helps deal with the exponential increase in com- putational problem sizes and the increased scale of parallelizing these problems." Making its inaugural appearance at the SC conference's 25th anniver- sary in 2013, the Test of Time Award recognizes the most transformative and inspiring research in the HPC commu- nity. The first Test of Time Award was presented to William Pugh, Emeritus Professor of Computer Science at the University of Maryland at College Park, at SC13 for his paper, "The Omega Project and Constraint Based Analysis Techniques in High Performance Computing." THE ANNUAL SUPERCOMPUTING AWARD PRESENTATION The ACM Gordon Bell Prize for 2014 will be presented on Thursday, November 20 as part of the SC Conference Awards Presentation beginning at 12:30 p.m. in the New Orleans Theater. Other awards to be presented include the SC14 Test of Time and the IEEE Technical Committee on Scalable Computing (TCSC) Young Investigators in Scalable Computing Awards; the SC14 Best Paper, Best Student Paper, and Best Poster Awards; George Michael Memorial HPC Ph.D. Fellowship; ACM Student Research Competition; and the Student Cluster Competition awards. This year, the recip- ient of the inaugural Best Visualization Award will also be recognized. Presenters are Barbara Chapman from the University of Houston and John Grosh from the Lawrence Livermore National Laboratory. This year's finalists for the ACM Gordon Bell Prize are: "Real-time Scalable Cortical Computing at 46 Giga- Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100,000× Reduction in Energy-to-Solution," with research led by Dharmendra S. Modha, IBM Fellow and IBM Chief Scientist – Brain-inspired Computing, and team including members from IBM and Cornell Tech; "24.77 Pflops on a Gravitational Tree-Code to Simulate the Milky Way Galaxy with 18600 GPUs," with their research led by Simon Portegies Zwart and Jeroen Bédorf of the Netherland's Leiden Observatory and team; "Anton 2: Raising the Bar for Performance and Programmability in a Special-Purpose Molecular Dynamics Supercomputer," with lead researcher David E. Shaw, of DE Shaw Research, and team; "Petascale High Order Dynamic Rupture Earthquake Simulations on Heterogeneous Supercomputers," a collaborative research project co-led by Michael Bader (TUM, Germany), Christian Pelties (LMU, Germany) and Alexander Heinecke (Intel, United States); and "Physics-based urban earthquake simulation enhanced by 10.7 BlnDOF x30 K time-step unstructured FE non-linear seismic wave simulation," with research led by the University of Tokyo's Tsuyoshi Ichimura.

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